Integrated circuitry incorporates and interconnects numerous electronic components. These electronic components may perform numerous functions and interact in complex ways. Some electronic components, referred to herein as "resources", are shared by one or more other components ("domains"), e.g., a digital signal processor ("DSP"). The resource is shared in that it may communicate with or serve numerous domains, albeit only one domain at any point in time. If two or more electronic domains were to attempt to use the shared resource simultaneously, data might be corrupted.
This gives rise to the concept of resource negotiation. Resource negotiation techniques are well known in chip design. Resource negotiation is performed to determine which domain is permitted to use the shared resource at a particular point in time in the event of conflict.
One common type of resource negotiation circuit uses a four-state state machine. For example, a chip may comprise two digital signal processor cores, DSP1 and DSP2 which share a common memory resource, such as a block of SRAM. A four-state state machine may be used in which the four states are represented by binary numbers 00, 01, 10, and 11, wherein state 00 indicates that neither DSP1 nor DSP2 is permitted to use the resource, i.e., neither "owns" the resource, 01 means that DSP1 owns the resource, 10 means that DSP2 owns the resource, and 11 is an inoperative state. The use of a four-state state machine is common because of the binary basis of digital logic, i.e., four states because four is a power of two. However, this leads to one inoperative state which tends to slow the resource negotiation circuit because the state machine must be "stepped" through the inoperative state to reach an operative state. Typically, the state machine is configured such that the inoperative state falls back to one of the other three operable states.
Also, the state machine is a "single clock edge" state machine, that is, it is configured to react on only one edge of each clock cycle, e.g., on the rising edge of the clock. If DSP1 and DSP2 issue sequential but nearly simultaneous requests, DSP1's request may be clocked into a resource negotiation circuit on the rising edge of the reference clock and DSP2's request may be delayed, after release of the resource by DSP1, while waiting for the next edge, e.g., rising edge, that controls the state machine. Delay, such as that caused while waiting for a next edge, is undesirable, particularly in high speed applications.
Additionally, a considerable amount of chip space is required to implement a single clock edge synchronous four-state resource negotiation circuit. Chip space is precious and more compact circuitry requiring less chip space is desirable, particularly in increasingly popular system-on-a-chip (SOC) designs.